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Dear Open Hub Users,

We’re excited to announce that we will be moving the Open Hub Forum to https://community.synopsys.com/s/black-duck-open-hub. Beginning immediately, users can head over, register, get technical help and discuss issue pertinent to the Open Hub. Registered users can also subscribe to Open Hub announcements here.


On May 1, 2020, we will be freezing https://www.openhub.net/forums and users will not be able to create new discussions. If you have any questions and concerns, please email us at info@openhub.net

Feedback Forum : Verilog interpreted as coq

Projects written in Verilog HDL get wrongly labeled as 'coq'. Example: https://www.openhub.net/p?q=mor1kx

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about 6 years ago