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Analyzed about 23 hours ago. based on code collected 1 day ago.

Project Summary

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Tags

cpu leon3 risc_v

In a Nutshell, ReonV...

This Project has No vulnerabilities Reported Against it

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Languages

VHDL
67%
C
22%
XML
5%
7 Other
6%

30 Day Summary

Jul 19 2022 — Aug 18 2022

12 Month Summary

Aug 18 2021 — Aug 18 2022

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