Analyzed
7 days
ago.
based on code collected
7 days
ago.
Project Summary
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
In a Nutshell, ReonV...
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took an estimated 128 years of effort (COCOMO model)
starting with its first commit in September, 2017
ending with its most recent commit over 1 year ago
Quick Reference
https://github.com/lcbcFoo/ReonV
This Project has No vulnerabilities Reported Against it
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