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Analyzed 7 days ago. based on code collected 7 days ago.

Project Summary

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Tags

cpu leon3 risc_v

In a Nutshell, ReonV...

This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
VHDL
67%
C
22%
XML
5%
7 Other
6%

30 Day Summary

Feb 29 2020 — Mar 30 2020

12 Month Summary

Mar 30 2019 — Mar 30 2020
  • 0 Commits
    Down -33 (100%) from previous 12 months
  • 0 Contributors
    Down -3 (100%) from previous 12 months

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