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Analyzed 1 day ago. based on code collected 1 day ago.

Project Summary

80186 compatible SystemVerilog CPU core and FPGA reference design

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Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

Languages?height=75&width=75
C++
60%
Ruby
14%
Python
10%
5 Other
16%

30 Day Summary

Feb 29 2020 — Mar 30 2020

12 Month Summary

Mar 30 2019 — Mar 30 2020
  • 0 Commits
    Down -86 (100%) from previous 12 months
  • 0 Contributors
    Down -3 (100%) from previous 12 months

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