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Project Summary

Simulate Verilog HDL without compiling to RTL. Instead, instantiate objects that run the HDL directly. A debugger that can then set breakpoints. single step, set watches, etc. then becomes feasable.

C# makes it easy to parse HDL and simulate. Prototype code and two simple testcases can be downloaded, but there is a lot more work to get to the final result.

IThe prototype is very basic, but I think it shows the feasibility of an IDE for hardware development that is analogous to a software IDE. Altera has Quartus II which is a start, but
leaves much manual checking up to the lead designer. I feel that the necessity to get the design to the RTL is what makes building the model as difficult as doing the design.
It is obvious that a computer can do a lot of things to reduce human error and effort. The problem is in identifying them.

My approach allows the very first module to be read in along with the initial statements to run a test case at day one of the design.

Module instantiation, conditional assignment, and concatination need to be added.

A user interface needs to be defined for module connectivity.

A method of design control/project management (IDE?) is needed.

Design coding guidelines checking is needed. VSome very good guidelines exist and should be integrated into a design tool.

A debugger is needed. (The F9, F10, F11 and watch functions)

In short, all of the software development issues addressed by the IDE have analogs in hardware design.

Tags

vsim

In a Nutshell, Verilog HDL OOP Simulation/IDE...

 No recognizable code

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 No recognizable code

Open Hub computes statistics on FOSS projects by examining source code and commit history in source code management systems. This project has code locations but that location contains no recognizable source code for Open Hub to analyze.

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