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Analyzed over 1 year ago. based on code collected almost 2 years ago.

Project Summary

A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.

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In a Nutshell, Cereon...

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

Languages?height=75&width=75
Java
67%
C++
25%
VHDL
5%
5 Other
3%

30 Day Summary

Jun 13 2019 — Jul 13 2019

12 Month Summary

Jul 13 2018 — Jul 13 2019

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