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Analyzed over 2 years ago. based on code collected over 2 years ago.

Project Summary

Allows electronics engineers and IC designers to create configurable RTL (VHDL/Verilog) IP cores and provides an interface for the user to set up core parameters.

CoreTML is based on a template system which is completely language-neutral and therefore can be used not only semiconductor-related projects.

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In a Nutshell, CoreTML framework...

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GNU Lesser General Public License v3.0 only
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This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
C++
80%
C
19%
7 Other
1%

30 Day Summary

Oct 18 2015 — Nov 17 2015

12 Month Summary

Nov 17 2014 — Nov 17 2015
  • 6 Commits
    Down -29 (82%) from previous 12 months
  • 1 Contributors
    Down 0 (0%) from previous 12 months

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