Analyzed
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based on code collected
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Project Summary
Allows electronics engineers and IC designers to create configurable RTL (VHDL/Verilog) IP cores and provides an interface for the user to set up core parameters.
CoreTML is based on a template system which is completely language-neutral and therefore can be used not only semiconductor-related projects.
In a Nutshell, CoreTML framework...
Quick Reference
svn://svn.code.sf.net/p/coretml/...
GNU Lesser General Public License v3.0 only
Permitted
Place Warranty
Commercial Use
Use Patent Claims
Modify
Distribute
Forbidden
Sub-License
Hold Liable
Required
Include Copyright
State Changes
Include Install Instructions
Include License
Distribute Original
Disclose Source
These details are provided for information only. No information here is legal advice and should not be used as such.
This Project has No vulnerabilities Reported Against it
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