Analyzed
over 2 years
ago.
based on code collected
about 3 years
ago.
Project Summary
Allows electronics engineers and IC designers to create configurable RTL (VHDL/Verilog) IP cores and provides an interface for the user to set up core parameters.
CoreTML is based on a template system which is completely language-neutral and therefore can be used not only semiconductor-related projects.
In a Nutshell, CoreTML framework...
GNU Lesser General Public License v3.0 only
Permitted
Commercial Use
Modify
Distribute
Place Warranty
Use Patent Claims
Forbidden
Sub-License
Hold Liable
Required
Distribute Original
Disclose Source
Include Copyright
State Changes
Include License
Include Install Instructions
These details are provided for information only. No information here is legal advice and should not be used as such.
This Project has No vulnerabilities Reported Against it
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