| Added Altera FIFO stuff to Verilog too |
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over 13 years ago
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| Fixed Altera build to support MegaWizard generation |
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over 13 years ago
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| Ooops, need XSVF files for testing |
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over 13 years ago
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| Move to using SVF files for intermediates rather than XSVF files |
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over 13 years ago
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| Fixed Altera JTAG problems in AVR firmware and add configurable endpoints to host-side code |
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over 13 years ago
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| Added FIFO wrappers, and Altera build |
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over 13 years ago
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| Fixing READMEs |
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over 13 years ago
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| Moved sync to fx2 |
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over 13 years ago
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| Added EPP stuff |
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over 13 years ago
|
| Renamed ports |
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over 13 years ago
|
| First release of EPP FIFO example |
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over 13 years ago
|
| EPP FX2 & AVR |
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over 13 years ago
|
| Move to lower level |
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over 13 years ago
|
| Licensing change: switch to LGPL |
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over 13 years ago
|
| Use top-level vendorCommands.h |
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over 13 years ago
|
| Switched to Basys2-compatible pin assignments |
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over 13 years ago
|
| First cut of AVR firmware |
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over 13 years ago
|
| First release of EPP-based CommFPGA implementation |
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over 13 years ago
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| First release of EPP-based cksum example |
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over 13 years ago
|
| Fixed typo |
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over 13 years ago
|
| Fixed typo |
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over 13 years ago
|
| Alignment foo |
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over 13 years ago
|
| Final pre-release fixes |
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over 13 years ago
|
| Ooops, forgot to revert |
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over 13 years ago
|
| Documentation |
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over 13 years ago
|
| Changed Register -> Channel |
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over 13 years ago
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| Removed dependency on basename |
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over 13 years ago
|
| Ooops, mistakenly committed temporary edit |
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over 13 years ago
|
| Renamed Register->Channel |
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More...
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over 13 years ago
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| Renaming SVF files in examples, etc |
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over 13 years ago
|
