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Analyzed 3 months ago. based on code collected 3 months ago.

Project Summary

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Tags

simulation veriloghdl verilog synthesis hdl simulate

In a Nutshell, Icarus Verilog...

This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
C++
66%
C
31%
4 Other
3%

30 Day Summary

Oct 27 2016 — Nov 26 2016

12 Month Summary

Nov 26 2015 — Nov 26 2016
  • 313 Commits
    Down -102 (24%) from previous 12 months
  • 14 Contributors
    Up + 6 (75%) from previous 12 months