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Analyzed 3 months ago. based on code collected 3 months ago.

Project Summary

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Tags

hdl simulate simulation synthesis verilog veriloghdl

In a Nutshell, Icarus Verilog...

This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
C++
66%
C
31%
4 Other
3%

30 Day Summary

Feb 8 2017 — Mar 10 2017

12 Month Summary

Mar 10 2016 — Mar 10 2017
  • 145 Commits
    Down -264 (64%) from previous 12 months
  • 15 Contributors
    Up + 6 (66%) from previous 12 months