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Analyzed about 10 hours ago. based on code collected about 10 hours ago.

Project Summary

Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

Tags

hdl simulate simulation synthesis verilog veriloghdl

GNU General Public License v2.0 or later
Permitted

Commercial Use

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Forbidden

Sub-License

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Required

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Disclose Source

Include Copyright

State Changes

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These details are provided for information only. No information here is legal advice and should not be used as such.

Project Security

Vulnerabilities per Version ( last 10 releases )

There are no reported vulnerabilities

Project Vulnerability Report

Security Confidence Index

Poor security track-record
Favorable security track-record

Vulnerability Exposure Index

Many reported vulnerabilities
Few reported vulnerabilities

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About Project Security

Languages

Languages?height=75&width=75
C++
65%
C
31%
4 Other
4%

30 Day Summary

Oct 31 2021 — Nov 30 2021

12 Month Summary

Nov 30 2020 — Nov 30 2021
  • 181 Commits
    Down -17 (8%) from previous 12 months
  • 5 Contributors
    Down -11 (68%) from previous 12 months

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