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Commits : Listings

Analyzed 3 months ago. based on code collected 3 months ago.
Nov 26, 2015 — Nov 26, 2016
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Fix for GitHub issue #105 - fully support SV macro escape sequences. Anon32 More... 9 months ago
Add basic support for parameters using typedefs Anon32 More... 9 months ago
Handle mixed continuous and non-blocking assignments to same vector. Anon32 More... 10 months ago
Fix for GitHub issue #103 - vvp assertion failure on part select propagation. Anon32 More... 10 months ago
Merge pull request #95 from orsonmmz/automatic_rebased D6236964e1275c2eace70b2f63c0edb7?&s=32&rating=pg&d=http%3a%2f%2fopenhub.net%2fanon32 More... 10 months ago
Extended fix for GitHub issue #99. Anon32 More... 10 months ago
Fix GitHub issue #99 - recv_vec4_pv not implemented for arithmetic functors. Anon32 More... 11 months ago
Fix for br974 - support SV types in non-ansi port declarations. Anon32 More... 11 months ago
Fix vlog95 target to handle delayed CA to vector part select. Anon32 More... 11 months ago
Fix for GitHub issue #96 - support mixed constant/variable delays in vvp. Anon32 More... 11 months ago
Refactor to use new pad_to_width/cast_to_width functions. Anon32 More... 11 months ago
Fix for GitHub issue #94 - enhance support for SystemVerilog size casting. Anon32 More... 11 months ago
Fix reference to undefined value (valgrind) Anon32 More... 11 months ago
Fix a cppcheck warning Anon32 More... 11 months ago
vhdlpp: Specify lifetime for variables. Anon32 More... 11 months ago
vhdlpp: Fixed automatic variables initalization in subprograms. Anon32 More... 11 months ago
Add check for explicit lifetime when initialising static variables. Anon32 More... 11 months ago
Added support for default subroutine lifetimes (SystemVerilog). Anon32 More... 11 months ago
Updated comment in tgt-vlog95 to reflect changes in variable initialization. Anon32 More... 11 months ago
Fix shadow warning. Anon32 More... 11 months ago