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Commits : Listings

Analyzed 18 days ago. based on code collected 18 days ago.
Mar 07, 2016 — Mar 07, 2017
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
[PERFECTIVE] Fixed diagram centering when zooming designs. Anon32 More... 5 months ago
[CLEANUP] Fixed linux compilation errors and warnings. Anon32 More... 5 months ago
[PERFECTIVE] Fixed an issue with connectivity graph creation with identical instance names. Anon32 More... 5 months ago
[ADDITIVE] Added an option to filter address space chains from a memory design (refs #80). Anon32 More... 5 months ago
[CORRECTIVE] Updated memory designer to recognize connections containing multiple master interfaces with contained address spaces (refs #80). Anon32 More... 5 months ago
[CORRECTIVE] Fixed an glitch that sometimes caused a crash, when Verilog was generated on a design with one or more undefined active views. Anon32 More... 5 months ago
[CORRECTIVE] Component instance Verilog writer now utilizes module name rather than component name. Anon32 More... 5 months ago
[PERFECTIVE] Added invert and tieoff value to show on logical port level in port map table. Anon32 More... 5 months ago
[PERFECTIVE] Simplified the view selection dialog so that the component instantiation is always the one that is referred by the chosen view. Anon32 More... 5 months ago
[CLEANUP] Relocated businterface general editor files to separate folder. Anon32 More... 5 months ago
[CLEANUP] Added missing comments and const definition. Anon32 More... 5 months ago
[PERFECTIVE] Adjusted port map auto-connect to less aggressive matching. Anon32 More... 5 months ago
[CORRECTIVE] Updated memory designer sub item name labels (refs #80). Anon32 More... 5 months ago
[CORRECTIVE] Updated memory designer graphics items (refs #80). Anon32 More... 5 months ago
[PERFECTIVE] Now generating register definitions is optional. Anon32 More... 5 months ago
[CLEANUP] Inserted comments missing from previous commit. Anon32 More... 5 months ago
[CORRECTIVE] Fixed glitches in Verilog module declaration detection. Anon32 More... 5 months ago
[PERFECTIVE] Added feature to follow symbolic links for files within library (refs #321). Anon32 More... 5 months ago
[CLEANUP] Cleaned verilog imported code a bit. Anon32 More... 5 months ago
[CORRECTIVE] Updated memory designer address space items (refs #80). Anon32 More... 5 months ago