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Moderate Activity

Commits : Listings

Analyzed 2 days ago. based on code collected 2 days ago.
Nov 10, 2017 — Nov 10, 2018
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
[ADDITIVE] Added invert-property in port maps to be written in Verilog generation. Anon32 More... 5 days ago
[CORRECTIVE] Fixed linux build issues. Anon32 More... 10 days ago
[CORRECTIVE] Fixed issue where removing VLVN items from library did not remove the XML file on disk. Anon32 More... 11 days ago
[PERFECTIVE] Improved VHDL generic import to recognize ranges and to set parameter type based on the data type in VHDL. Anon32 More... 11 days ago
[CORRECTIVE] Improved VHDL import to recognize port vector boundaries with expressions containing parentheses. Anon32 More... 11 days ago
[CORRECTIVE] Fixed parameter parsing in Verilog import. Anon32 More... 14 days ago
[CORRECTIVE] Restored graying text in register file table if isPresent is false. Anon32 More... 28 days ago
Merge branch 'DanChianucci-feature/isPresentOverlap' Anon32 More... 28 days ago
Merge branch 'feature/isPresentOverlap' of git://github.com/DanChianucci/kactus2dev into DanChianucci-feature/isPresentOverlap Anon32 More... 28 days ago
[CLEANUP] Removed obsolete files. Anon32 More... 29 days ago
[PERFECTIVE] Separated registers and register files into own tables. Anon32 More... 29 days ago
[CLEANUP] Added comments and minor changes to conform to coding conventions. Anon32 More... about 1 month ago
[CORRECTIVE] Updated VS project files. Anon32 More... about 1 month ago
Merge pull request #10 from DanChianucci/feature/regfile Anon32 More... about 1 month ago
Merge branch 'pr10_merge' into feature/regfile Anon32 More... about 1 month ago
[CORRECTIVE] Fixed an issue, where ad-hoc connections were removed for ports already included in an interface in Verilog generation. Anon32 More... about 1 month ago
[CORRECTIVE] Fixed CSV import/export with multiline comments. Anon32 More... about 1 month ago
[CORRECTIVE] Fixed writing wire array bounds in Verilog generation. [CORRECTIVE] Fixed writing wiring for ports connected in multiple interfaces (refs #343). Anon32 More... about 1 month ago
Merge branch 'master' of github.com:kactus2/kactus2dev Anon32 More... 3 months ago
Update CONTRIBUTING.md Anon32 More... 3 months ago
[CORRECTIVE] Fixed an issue with Design parameters with choices. Anon32 More... 3 months ago
[PERFECTIVE] Updated help for expressions. Anon32 More... 3 months ago
[CORRECTIVE] Fixed VHDL generic value passing to instances. [CORRECTIVE] Fixed parsing description in VHDL import. [CLEANUP] Improved readability in VHDL Generator. Anon32 More... 3 months ago
[ADDITIVE] Added support for bit-wise ~ operator (negate) in expressions. Anon32 More... 3 months ago
Merge pull request #12 from DanChianucci/feature/expressionParser Anon32 More... 4 months ago
Added support for Shift (<< >>), modulus (%), Boolean (&& ||) and bitwise (& | ^) operators. Anon32 More... 4 months ago
Added isPresentChecking to has...Error functions as well as the find...Errors functions Anon32 More... 4 months ago
AddressBlock / Register / Field overlap shouldn't be validated if either of the item's "isPresent" field evaluates to false. (See IEEE 1685-2014 C.10.2) Anon32 More... 4 months ago
Register File Graphic Item takes the address width of its parent Anon32 More... 4 months ago
[CORRECTIVE] Fixed Linux compilation. Anon32 More... 5 months ago