1
I Use This!
Moderate Activity

Commits : Listings

Analyzed about 2 hours ago. based on code collected about 2 hours ago.
Dec 16, 2017 — Dec 16, 2018
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
[CORRECTIVE] Fixed issues in Linux build Anon32 More... 3 days ago
[CORRECTIVE] Fixed showing the details of plugins in the settings. Anon32 More... 4 days ago
[ADDITIVE] Added initial editor for vendor extensions in component. Anon32 More... 11 days ago
[CORRECTIVE] Fixed re-reading sticky notes into design which previously caused the application to crash. Anon32 More... 12 days ago
[PERFECTIVE] Added validation for all field resets and updated tests. Anon32 More... 17 days ago
Merge pull request #19 from DanChianucci/feature/multireset Anon32 More... 17 days ago
IPXACt Models Now Support Reading and Writing Multiple reset values. Editors are unaware of multiple resets, and will continue to act as iff only the last reset in the list exists. Anon32 More... 18 days ago
Merge branch 'master' of github.com:kactus2/kactus2dev Anon32 More... 18 days ago
[CORRECTIVE] Adjusted Verilog generation to remove unconnected wires to module instances. Anon32 More... 18 days ago
Merge pull request #17 from DanChianucci/fix/unConstrained Anon32 More... 18 days ago
Changed unConstrained to unconstrained as per spec. Anon32 More... 19 days ago
Merge pull request #16 from ithinuel/fix_strlen_segv Anon32 More... 20 days ago
fix segfaults in strlen. Anon32 More... 21 days ago
Merge remote-tracking branch 'remotes/origin/master' Anon32 More... 26 days ago
[CORRECTIVE] Fixed writing array and vector bounds in Verilog generation. Anon32 More... 26 days ago
[CORRECTIVE] Fixed parsing array and vector bounds in Verilog import. Anon32 More... about 1 month ago
[CORRECTIVE] Fixed validation of parameter value compared to minimum and maximum values. Anon32 More... about 1 month ago
[ADDITIVE] Added invert-property in port maps to be written in Verilog generation. Anon32 More... about 1 month ago
[CORRECTIVE] Fixed linux build issues. Anon32 More... about 1 month ago
[CORRECTIVE] Fixed issue where removing VLVN items from library did not remove the XML file on disk. Anon32 More... about 2 months ago
[PERFECTIVE] Improved VHDL generic import to recognize ranges and to set parameter type based on the data type in VHDL. Anon32 More... about 2 months ago
[CORRECTIVE] Improved VHDL import to recognize port vector boundaries with expressions containing parentheses. Anon32 More... about 2 months ago
[CORRECTIVE] Fixed parameter parsing in Verilog import. Anon32 More... about 2 months ago
[CORRECTIVE] Restored graying text in register file table if isPresent is false. Anon32 More... 2 months ago
Merge branch 'DanChianucci-feature/isPresentOverlap' Anon32 More... 2 months ago
Merge branch 'feature/isPresentOverlap' of git://github.com/DanChianucci/kactus2dev into DanChianucci-feature/isPresentOverlap Anon32 More... 2 months ago
[CLEANUP] Removed obsolete files. Anon32 More... 2 months ago
[PERFECTIVE] Separated registers and register files into own tables. Anon32 More... 2 months ago
[CLEANUP] Added comments and minor changes to conform to coding conventions. Anon32 More... 2 months ago
[CORRECTIVE] Updated VS project files. Anon32 More... 2 months ago