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Kestrel Computer

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Commits : Listings

Analyzed about 6 hours ago. based on code collected about 10 hours ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Apr 24, 2023 — Apr 24, 2024 Showing page 1 of 37 Search / Filter on:
WIP: still adding async interrupt support	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Internal trap dispatching/handling	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Implement trap detection and external response	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Feature parity with S16X4A attained	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
ICALL	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
LCALL and FBM/SBM	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Feature parity with Steamer-16	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Support LIT opcode	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
First steps for X4B CPU	sam-falvo as Samuel A. Falvo II	More...				about 4 years ago
Fix off-by-one-cycle errors	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Remove dead code	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Integrate register feedback/passthrough into decoder	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Forwarder -- part of the register forwarding unit.	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Register the data to write out to memory.	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Generate wbmsel_o internally.	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Initial code for basic integration test	sam-falvo as Samuel A. Falvo II	More...				over 6 years ago
Implement store instructions	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Refine bench to use more realistic timing model.	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Commence work on instruction decoder	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Test cases for execute stage	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Introduce first cut at execute stage	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
When mem_i is asserted, completely overwrite state.	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
clean up docs	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
WIP: Simplifying EX/MEM stage interface	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Support unsigned memory ops	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Fix STALL_I bug on 1st cycle of a txn	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Propegate destination register to next pipeline stage	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Forgot an include	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Generate new RWE_O signal; distinguish bytes from hwords.	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago
Make sel_i part of the registered command	sam-falvo as Samuel A. Falvo II	More...				almost 7 years ago

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