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Commits : Listings

Analyzed about 6 hours ago. based on code collected about 12 hours ago.
Apr 23, 2023 — Apr 23, 2024
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
[SystemZ][z/OS] Make z/OS personality function known (#89679)
Kai Nacke
More... about 12 hours ago
Reapply "[Clang][Sema] placement new initializes typedef array with correct size (#83124)" (#89036)
mahtohappy
More... about 12 hours ago
[RISCV] Add additional mul strength reduction coverage with xtheadba
Philip Reames
More... about 12 hours ago
[AMDGPU] Fix GFX12 encoding of s_wait_event export_ready (#89622)
Jay Foad
More... about 13 hours ago
[gn build] Port 70d3ddb280ea
LLVM GN Syncbot
More... about 13 hours ago
[RemoveDIs][MLIR] Don't process debug records in the LLVM-IR translator (#89735)
Stephen Tozer
More... about 13 hours ago
[SLP]Fix PR89635: do not try to vectorize single-gather alternate node.
Alexey Bataev
More... about 14 hours ago
[libc++] Add some private headers to libcxx.imp (#89568)
Takuto Ikuta
More... about 14 hours ago
[Frontend][OpenMP] Add functions for checking construct type (#87258)
Krzysztof Parzyszek
More... about 14 hours ago
[VPlan] Ignore incoming values with constant false mask. (#89384)
Florian Hahn
More... about 14 hours ago
[Clang][Parser] Don't always destroy template annotations at the end of a declaration (#89494)
Younan Zhang
More... about 14 hours ago
[X86] getTargetShuffleMask - update to take a SDValue instead of a SDNode. NFC.
Simon Pilgrim
More... about 14 hours ago
[DAGCombiner] Fix miscompile bug in combineShiftOfShiftedLogic (#89616)
Björn Pettersson
More... about 15 hours ago
[Flang][OpenMP] Add restriction about subobjects to firstprivate and … (#89608)
Kiran Chandramohan
More... about 15 hours ago
[SelectionDAG] Mark frame index as "aliased" at argument copy elison (#89712)
Björn Pettersson
More... about 15 hours ago
[InstCombine] Fold fcmp into select (#86482)
Yingwei Zheng
More... about 15 hours ago
[clang-tidy] Avoid overflow when dumping unsigned integer values (#85060)
ealcdan
More... about 16 hours ago
[ARM][AArch64] Split out processor and feature tablegen defs [NFC] (#88282)
Tomas Matheson
More... about 16 hours ago
[TableGen] Fix ReplaceRegAction RTTI Kind
pvanhout
More... about 16 hours ago
[VPlan] Skip extending ICmp results in trunateToMinimalBitwidth.
Florian Hahn
More... about 16 hours ago
[VectorCombine] foldShuffleOfShuffles - add missing arguments to getShuffleCost calls.
Simon Pilgrim
More... about 16 hours ago
[LLVM][CodeGen][SVE] rev(whilelo(a,b)) -> whilehi(b,a). (#88294)
Paul Walker
More... about 16 hours ago
RenameIndependentSubregs: Add missing sub-range for new IMPLICIT_DEFs (#89050)
Petar Avramovic
More... about 16 hours ago
[LLVM][CodeGen][AArch64] Simplify lowering for predicate inserts. (#89072)
Paul Walker
More... about 16 hours ago
[CostModel][X86] Broadcast shuffles can be free if they are from a one-use load
Simon Pilgrim
More... about 17 hours ago
[mlir][aarch64] Remove LIT config for lli (#89545)
Andrzej Warzyński
More... about 17 hours ago
[CostModel][X86] Add costs test coverage for broadcast loads
Simon Pilgrim
More... about 17 hours ago
[mlir][linalg] Move transpose_matmul to targeted transform op (#89717)
Cullen Rhodes
More... about 17 hours ago
[VectorCombine][X86] Add test showing foldShuffleOfShuffles folding shuffles that would be better separate
Simon Pilgrim
More... about 17 hours ago
[bazel] Add a bazel flag to enable building MLIR with CUDA support (#88856)
Adam Paszke
More... about 17 hours ago