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Commits : Listings

Analyzed 1 day ago. based on code collected 1 day ago.
Mar 27, 2023 — Mar 27, 2024
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
FW 1.7 - added minila_pkg.vhd More... over 17 years ago
Added trigger edge detectors, optimized timing. More... over 17 years ago
Firmware ver 2.2 - removed timebase - added pretrigger - added edge detectors More... over 17 years ago
Added saving of INI file, parameters case sensitive, reporting of unknown parameters, data are read first from minila before saving. More... over 18 years ago
Updated to support firmwares 1,6 and 2.1. Support for subversions 80, 40 and 20 added. Added VCD file output. Definitions of own signal/bus names possible via INI file. More... over 18 years ago
Added header More... over 18 years ago
Updated to respect design modifications More... over 18 years ago
Initial revision More... over 18 years ago
*** empty log message *** More... over 18 years ago
Net clk_o moved from P31 to P26. More... over 18 years ago
Added signal inv_trig (invert internal trigger). More... over 18 years ago
no changes More... over 18 years ago
FW 2.1, added signal inv_trig. More... over 18 years ago
Corrected extrig_en and extrig_val assignment, added signal inv_trig. More... over 18 years ago
Firmware 2.1 More... over 18 years ago
*** empty log message *** More... over 18 years ago
Net clk_100 renamed to clk_in, net clk_o moved from P31 to P26. More... over 18 years ago
External and internal trigger input registered. More... over 18 years ago
no changes More... over 18 years ago
Input clk_100 renamed to clk_in, signal postrig_on renamed to pretrig_off, added signal inv_trig, assignments to signal st in the state machine inverted, sample_cnt_wm removed from condition at state st_prefill. More... over 18 years ago
Signal postrig_on renamed to pretrig_off, corrected extrig_val and extrig_en assignment, added signal inv_trig. More... over 18 years ago
Firmware 1.6 More... over 18 years ago
Communication protocol More... almost 19 years ago
*** empty log message *** More... almost 19 years ago
Initial revision More... almost 19 years ago
generic TRIGGER_WIDTH removed More... almost 19 years ago
timebase for 10Hz, 20Hz and 50Hz removed polarity of output clock selectable glitch-free switching to read clock More... almost 19 years ago
posttrigger counter changed to pretrigger burst-counter removed SRAM CE now always active More... almost 19 years ago
added stop of sampling functionality added pretrigger data output for SRAM registered generic TRIGGER_WIDTH removed FW version set to 1.5 changes of signal names More... almost 19 years ago
EPP access synchronized to miniLA clock added auto-incrementation of bytesel and address counter added STOP functionality, rising/falling edge support posttrigger register changed to pretrigger reg. and resized to 4bits. unused registers removed reading of data from address 12-15 removed outputs are in Hi-Z when reading unimplemented registers More... almost 19 years ago