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MiniLA - logic analyzer SW & HW
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Inactive
Commits
: Listings
Analyzed
1 day
ago. based on code collected
1 day
ago.
Mar 27, 2023 — Mar 27, 2024
Showing page 1 of 2
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FW 1.7 - added minila_pkg.vhd
jsmrz
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over 17 years ago
Added trigger edge detectors, optimized timing.
jsmrz
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over 17 years ago
Firmware ver 2.2 - removed timebase - added pretrigger - added edge detectors
jsmrz
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over 17 years ago
Added saving of INI file, parameters case sensitive, reporting of unknown parameters, data are read first from minila before saving.
jsmrz
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over 18 years ago
Updated to support firmwares 1,6 and 2.1. Support for subversions 80, 40 and 20 added. Added VCD file output. Definitions of own signal/bus names possible via INI file.
jsmrz
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over 18 years ago
Added header
jsmrz
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over 18 years ago
Updated to respect design modifications
jsmrz
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over 18 years ago
Initial revision
jsmrz
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over 18 years ago
*** empty log message ***
jsmrz
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over 18 years ago
Net clk_o moved from P31 to P26.
jsmrz
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over 18 years ago
Added signal inv_trig (invert internal trigger).
jsmrz
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over 18 years ago
no changes
jsmrz
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over 18 years ago
FW 2.1, added signal inv_trig.
jsmrz
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over 18 years ago
Corrected extrig_en and extrig_val assignment, added signal inv_trig.
jsmrz
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over 18 years ago
Firmware 2.1
jsmrz
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over 18 years ago
*** empty log message ***
jsmrz
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over 18 years ago
Net clk_100 renamed to clk_in, net clk_o moved from P31 to P26.
jsmrz
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over 18 years ago
External and internal trigger input registered.
jsmrz
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over 18 years ago
no changes
jsmrz
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over 18 years ago
Input clk_100 renamed to clk_in, signal postrig_on renamed to pretrig_off, added signal inv_trig, assignments to signal st in the state machine inverted, sample_cnt_wm removed from condition at state st_prefill.
jsmrz
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over 18 years ago
Signal postrig_on renamed to pretrig_off, corrected extrig_val and extrig_en assignment, added signal inv_trig.
jsmrz
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over 18 years ago
Firmware 1.6
jsmrz
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over 18 years ago
Communication protocol
jsmrz
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almost 19 years ago
*** empty log message ***
jsmrz
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almost 19 years ago
Initial revision
jsmrz
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almost 19 years ago
generic TRIGGER_WIDTH removed
jsmrz
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almost 19 years ago
timebase for 10Hz, 20Hz and 50Hz removed polarity of output clock selectable glitch-free switching to read clock
jsmrz
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almost 19 years ago
posttrigger counter changed to pretrigger burst-counter removed SRAM CE now always active
jsmrz
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almost 19 years ago
added stop of sampling functionality added pretrigger data output for SRAM registered generic TRIGGER_WIDTH removed FW version set to 1.5 changes of signal names
jsmrz
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almost 19 years ago
EPP access synchronized to miniLA clock added auto-incrementation of bytesel and address counter added STOP functionality, rising/falling edge support posttrigger register changed to pretrigger reg. and resized to 4bits. unused registers removed reading of data from address 12-15 removed outputs are in Hi-Z when reading unimplemented registers
jsmrz
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almost 19 years ago
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