Project Summary
This is a Verilog description of a UART with a simple, documented interface.
This module was created as a result of my own need for a UART (serial line I/O) component and frustration at the difficulty of integrating the existing available components in to my own project. All the open source UART modules I found were difficult to interface with, usually due to being more clever than I wanted them to be, and had poor documentation for their interfaces. They were also generally written in VHDL, which since I've never written VHDL made it a little difficult to read to work out the interfacing issues for myself. The frustration of finding such a simple component so hard to use prompted the decision to create my own, and document it for beginners like myself.
In a Nutshell, Open Source Documented Verilog UART...
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These details are provided for information only. No information here is legal advice and should not be used as such.
This Project has No vulnerabilities Reported Against it
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