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Analyzed 17 days ago. based on code collected 17 days ago.

Project Summary

A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.

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In a Nutshell, RTUCR...

This Project has No vulnerabilities Reported Against it

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C
98%
Perl
2%

30 Day Summary

Oct 5 2018 — Nov 4 2018

12 Month Summary

Nov 4 2017 — Nov 4 2018

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