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I Use This!
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Commits : Listings

Analyzed about 12 hours ago. based on code collected 2 days ago.
Sep 14, 2024 — Sep 14, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
upadting m_Ext using fixes from c-class More... over 6 years ago
adapting alu from c-class More... over 6 years ago
renaming stage2 More... over 6 years ago
adding initialization sequence of RegFile More... over 6 years ago
access rf independent of whether you are enquing or not More... over 6 years ago
integrating new registerfile module More... over 6 years ago
adding new registerfile module with bypass functionality More... over 6 years ago
fixed indentation More... over 6 years ago
commenting out old types More... over 6 years ago
using eclint over all modules for indentation fix More... over 6 years ago
fixed indentation with eclint More... over 6 years ago
adding in trigger based structures More... over 6 years ago
minor beautification More... over 6 years ago
adding rename-script of vrilog post processing More... over 6 years ago
bumping devices More... over 6 years ago
split the tx into multiple interfaces More... over 6 years ago
updated decoder based on changes from c-class More... over 6 years ago
redefined types for stage1 More... over 6 years ago
adding exception and interrupt cause as macros More... over 6 years ago
updated soc_config parameters More... over 6 years ago
updated makefile based on c-class updates More... over 6 years ago
adding new stage1 types More... over 6 years ago
multiple fixes More... over 6 years ago
removing i-cache code More... over 6 years ago
bumping common_bsv More... over 6 years ago
changing tags of the runner More... over 6 years ago
no longer use this repo. More... over 6 years ago
Merge branch 'paddr_resetpc_as_macros' into 'master' More... over 6 years ago
enabling io_xactor only when cache present More... over 6 years ago
enabling IO master only if cache present More... over 6 years ago