Analyzed
3 days
ago.
based on code collected
3 days
ago.
Project Summary
Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
In a Nutshell, Signs...
Quick Reference
https://svn.code.sf.net/p/signs/...
BSD 4-clause (University of California-Specific)
Permitted
Commercial Use
Modify
Distribute
Place Warranty
Forbidden
Use Trademarks
Hold Liable
Required
Include Copyright
Include License
These details are provided for information only. No information here is legal advice and should not be used as such.
This Project has No vulnerabilities Reported Against it
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