Analyzed
about 1 year
ago.
based on code collected
over 1 year
ago.
Project Summary
Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
In a Nutshell, Signs...
Quick Reference
https://svn.code.sf.net/p/signs/...
BSD 4-clause (University of California-Specific)
Permitted
Commercial Use
Modify
Distribute
Place Warranty
Forbidden
Hold Liable
Use Trademarks
Required
Include Copyright
Include License
These details are provided for information only. No information here is legal advice and should not be used as such.
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Poor security track-record
Favorable security track-record
Vulnerability Exposure Index
Many reported vulnerabilities
Few reported vulnerabilities
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