S

sim-sim

Settings | Report Duplicate

0

I Use This!

Activity Not Available

Analyzed over 2 years ago. based on code collected about 6 years ago.

Project Summary

HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

Tags

No tags have been added

In a Nutshell, sim-sim...

...
has had 608 commits made by 1 contributors
representing 115,420 lines of code
...
is mostly written in C++
with a low number of source code comments
...
has a well established, mature codebase
maintained by nobody
with stable Y-O-Y commits
...
took an estimated 29 years of effort (COCOMO model)
starting with its first commit in July, 2006
ending with its most recent commit almost 10 years ago

Quick Reference

Code Locations:

:pserver:anonymous:@sim-sim.cvs....

Similar Projects:

Become the first manager for sim-sim

This Project has No vulnerabilities Reported Against it

Did You Know...

...
there are over 3,000 projects on the Open Hub with security vulnerabilities reported against them
...
data presented on the Open Hub is available through our API
...
nearly 1 in 3 companies have no process for identifying, tracking, or remediating known open source vulnerabilities
...
check out hot projects on the Open Hub

Code

Lines of Code

Activity

Commits per Month

Community

Contributors per Month

Languages

C++	81%
Make	17%
2 Other	2%

30 Day Summary

Jun 18 2016 — Jul 18 2016

0 Commits
0 Contributors

12 Month Summary

Jul 18 2015 — Jul 18 2016

0 Commits
0 Contributors

Most Recent Contributors

Ratings

Be the first to rate this project

Click to add your rating

Review this Project!