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Analyzed over 1 year ago. based on code collected over 4 years ago.

Project Summary

HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

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Languages

Languages?height=75&width=75
C++
81%
Make
17%
2 Other
2%

30 Day Summary

Jun 18 2016 — Jul 18 2016

12 Month Summary

Jul 18 2015 — Jul 18 2016

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