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sim-sim

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Analyzed over 1 year ago. based on code collected over 4 years ago.

Project Summary

HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

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In a Nutshell, sim-sim...

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has had 608 commits made by 1 contributors
representing 115,420 lines of code
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is mostly written in C++
with a low number of source code comments
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has a well established, mature codebase
maintained by nobody
with stable Y-O-Y commits
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took an estimated 29 years of effort (COCOMO model)
starting with its first commit in July, 2006
ending with its most recent commit over 8 years ago

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Code Locations:

:pserver:anonymous:@sim-sim.cvs....

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This Project has No vulnerabilities Reported Against it

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Code

Lines of Code

Activity

Commits per Month

Community

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C++	81%
Make	17%
2 Other	2%

30 Day Summary

Jun 18 2016 — Jul 18 2016

0 Commits
0 Contributors

12 Month Summary

Jul 18 2015 — Jul 18 2016

0 Commits
0 Contributors

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