Source Navigator for Verilog

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Analyzed over 1 year ago. based on code collected over 2 years ago.

Project Summary

Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav

In a Nutshell, Source Navigator for Verilog...

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has had 20 commits made by 1 contributors
representing 24,300 lines of code
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is mostly written in C++
with a well-commented source code
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has a codebase with a very short history
maintained by nobody
with stable Y-O-Y commits
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took an estimated 6 years of effort (COCOMO model)
starting with its first commit in December, 2000
ending with its most recent commit about 20 years ago

Quick Reference

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This Project has No vulnerabilities Reported Against it

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