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Project Summary

Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav

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In a Nutshell, Source Navigator for Verilog...

This Project has No vulnerabilities Reported Against it

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Languages

C++
83%
shell script
6%
Autoconf
5%
3 Other
6%

30 Day Summary

Sep 16 2018 — Oct 16 2018

12 Month Summary

Oct 16 2017 — Oct 16 2018

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