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Analyzed 9 months ago. based on code collected 9 months ago.

Project Summary

The aim of this project is to provide a framework for investigating hardware transactional memory (HTM) within the simics full-system simulator, using the x86 architecture. The project aims to achieve the following:

Provide a simple module to start working with transactional memory. Ability to send events to an external event monitor/simulator. Regression status: STAMP passes (with caveat noted in issue 1)

The code here is very early alpha if not pre-alpha... you've been warned

If you're still keen to try it, please follow the GettingStarted guide to learn how to use transmem. If you do use transmem please let us know, thanks.

Tags

simulation transactional simics memory multicore manycore

In a Nutshell, transmem...

This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
C++
53%
Java
18%
C
19%
5 Other
10%

30 Day Summary

Apr 9 2016 — May 9 2016

12 Month Summary

May 9 2015 — May 9 2016

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