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Analyzed over 2 years ago. based on code collected about 6 years ago.

Project Summary

Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.

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Languages

C++
78%
C
15%
5 Other
7%

30 Day Summary

Jun 23 2016 — Jul 23 2016

12 Month Summary

Jul 23 2015 — Jul 23 2016

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