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Commits : Listings

Analyzed about 4 hours ago. based on code collected about 4 hours ago.
Aug 13, 2024 — Aug 13, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Migrate fifo.core to CAPI2 More... about 5 years ago
Bump version More... over 7 years ago
Add backend and new core file for Xilinx FIFOE1 More... over 7 years ago
Added some basic documentation More... over 7 years ago
Add FIFO testbench More... over 7 years ago
Rename FIFO fwft testbench module More... over 7 years ago
Add testbench for dual clock FIFO More... over 7 years ago
Rename fifo_reader to fifo_fwft_reader More... over 7 years ago
Prepare for release More... over 8 years ago
Reinsert translate_off statement removed by mistake More... over 8 years ago
Prepare for release More... over 8 years ago
Expose testbench depth_width parameter More... over 8 years ago
fifo_reader: Avoid using systemverilog function More... over 8 years ago
Change illegal parameter values to warnings More... over 8 years ago
fifo_fwft: Whitespace cleanup More... over 8 years ago
Remove unused cnt output More... over 8 years ago
Add contraints file More... almost 9 years ago
Update .core and prepare for release More... almost 9 years ago
Silence width mismatch warnings More... almost 9 years ago
Refactor fifo_fwft More... almost 11 years ago
Add dual clock fifo to fifo.core More... almost 11 years ago
Add dual clock fifo More... almost 11 years ago
fifo.v: Bugfix More... almost 11 years ago
TB: Add timeout and mask writes to full FIFO More... almost 11 years ago
Update FIFO and DPRAM blocks with read enable More... almost 11 years ago
Allow writes when FIFO is full More... almost 11 years ago
Add configurable read rate More... almost 11 years ago
Added more verbose error reporting More... almost 11 years ago
Added timeout in FIFO reader More... almost 11 years ago
Fix FIFO writer More... almost 11 years ago