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Commits : Listings

Analyzed about 3 hours ago. based on code collected about 6 hours ago.
Apr 19, 2023 — Apr 19, 2024
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Migrate fifo.core to CAPI2 More... almost 4 years ago
Bump version More... over 6 years ago
Add backend and new core file for Xilinx FIFOE1 More... over 6 years ago
Added some basic documentation More... over 6 years ago
Add FIFO testbench More... over 6 years ago
Rename FIFO fwft testbench module More... over 6 years ago
Add testbench for dual clock FIFO More... over 6 years ago
Rename fifo_reader to fifo_fwft_reader More... over 6 years ago
Prepare for release More... almost 7 years ago
Reinsert translate_off statement removed by mistake More... almost 7 years ago
Prepare for release More... about 7 years ago
Expose testbench depth_width parameter More... about 7 years ago
fifo_reader: Avoid using systemverilog function More... about 7 years ago
Change illegal parameter values to warnings More... about 7 years ago
fifo_fwft: Whitespace cleanup More... about 7 years ago
Remove unused cnt output More... about 7 years ago
Add contraints file More... over 7 years ago
Update .core and prepare for release More... over 7 years ago
Silence width mismatch warnings More... over 7 years ago
Refactor fifo_fwft More... over 9 years ago
Add dual clock fifo to fifo.core More... over 9 years ago
Add dual clock fifo More... over 9 years ago
fifo.v: Bugfix More... over 9 years ago
TB: Add timeout and mask writes to full FIFO More... over 9 years ago
Update FIFO and DPRAM blocks with read enable More... over 9 years ago
Allow writes when FIFO is full More... over 9 years ago
Add configurable read rate More... over 9 years ago
Added more verbose error reporting More... over 9 years ago
Added timeout in FIFO reader More... over 9 years ago
Fix FIFO writer More... over 9 years ago