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Analyzed about 10 hours ago. based on code collected about 10 hours ago.

Project Summary

VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

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In a Nutshell, VeriWell Verilog Simulator...

This Project has No vulnerabilities Reported Against it

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Autoconf
31%
C++
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C
20%
5 Other
20%

30 Day Summary

Mar 23 2018 — Apr 22 2018

12 Month Summary

Apr 22 2017 — Apr 22 2018

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