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Hyena VHDL Triangle Rasterizer

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Analyzed about 6 hours ago. based on code collected about 6 hours ago.

Project Summary

My bachelor thesis project; A tile-based triangle rasterizer in hardware. (2005)

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In a Nutshell, Hyena VHDL Triangle Rasterizer...

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has had 1 commits made by 1 contributors
representing 1,482 lines of code
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is mostly written in VHDL
with an average number of source code comments
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has a codebase with a very short history
maintained by nobody
with stable Y-O-Y commits
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took an estimated 1 years of effort (COCOMO model)
starting with its first commit in February, 2012
ending with its most recent commit about 9 years ago

Quick Reference

Code Locations:

git://github.com/quarnster/Hyena...

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This Project has No vulnerabilities Reported Against it

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VHDL	100%

30 Day Summary

Mar 20 2021 — Apr 19 2021

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12 Month Summary

Apr 19 2020 — Apr 19 2021

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