Olof Kindgren

Gothenburg, Sweden
 

Managed Projects

edalize

  Analyzed 1 day ago

An abstraction library for interfacing EDA tools

15.6K lines of code

16 current contributors

23 days since last commit

1 users on Open Hub

Low Activity
0.0
 
I Use This

wb_streamer

  Analyzed 1 day ago

Wishbone component for converting data streams to wishbone transactions

1.16K lines of code

0 current contributors

over 8 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

fusesoc

  Analyzed 1 day ago

FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

6.42K lines of code

10 current contributors

about 2 months since last commit

1 users on Open Hub

Low Activity
0.0
 
I Use This
Licenses: No declared licenses

ipyxact

  Analyzed 1 day ago

Python-based IP-XACT parser

52.7K lines of code

3 current contributors

about 2 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

verilog-fifo

  Analyzed about 17 hours ago

Generic FIFO implementation with optional FWFT

1.09K lines of code

0 current contributors

about 5 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

orpsoc-cores

  Analyzed about 7 hours ago

Core description files for ORPSoCv3

265K lines of code

0 current contributors

almost 7 years since last commit

1 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

vlog_tb_utils

  Analyzed about 12 hours ago

Verilog test bench utilities

157 lines of code

0 current contributors

almost 4 years since last commit

0 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

elf-loader

  Analyzed about 21 hours ago

VPI library to load ELF files from verilog test benches

359 lines of code

0 current contributors

over 4 years since last commit

0 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses

LED to Believe

  Analyzed 1 day ago

Example LED blinking project for your FPGA dev board of choice

1.08K lines of code

8 current contributors

about 1 month since last commit

0 users on Open Hub

Low Activity
0.0
 
I Use This

SweRVolf

  Analyzed about 3 hours ago

FuseSoC-based SoC for SweRV EH1

31.4K lines of code

1 current contributors

8 months since last commit

0 users on Open Hub

Very Low Activity
0.0
 
I Use This
Licenses: No declared licenses