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Analyzed about 13 hours ago. based on code collected about 13 hours ago.

Project Summary

implement a siple Caldulator on an Altera Stratix EP1S25F672C6

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In a Nutshell, FPGA-Calculator...

This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
VHDL
85%
XML
8%
TeX/LaTeX
6%
2 Other
1%

30 Day Summary

Dec 18 2021 — Jan 17 2022

12 Month Summary

Jan 17 2021 — Jan 17 2022

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