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Analyzed 1 day ago. based on code collected 1 day ago.

Project Summary

implement a siple Caldulator on an Altera Stratix EP1S25F672C6

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In a Nutshell, FPGA-Calculator...

This Project has No vulnerabilities Reported Against it

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Languages

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VHDL
87%
XML
8%
3 Other
5%

30 Day Summary

Sep 21 2019 — Oct 21 2019

12 Month Summary

Oct 21 2018 — Oct 21 2019

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