Icarus Verilog

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Analyzed about 24 hours ago. based on code collected 1 day ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Apr 30, 2023 — Apr 30, 2024 Showing page 335 of 336 Search / Filter on:
Support null target for generating no output.	steve	More...				over 25 years ago
Add startup after initialization.	steve	More...				over 25 years ago
Support the start() method.	steve	More...				over 25 years ago
Proberly print vectors in binary.	steve	More...				over 25 years ago
Function to calculate wire initial value.	steve	More...				over 25 years ago
Parse more UDP input edge descriptions.	steve	More...				over 25 years ago
VVM support for small sequential UDP objects.	steve	More...				over 25 years ago
Fully elaborate Sequential UDP behavior.	steve	More...				over 25 years ago
Support the include directive.	steve	More...				over 25 years ago
Fix 2pin logic gates.	steve	More...				over 25 years ago
Generate OBUF or IBUF attributes (and the gates to garry them) where a wire is a pad. This involved figuring out enough of the netlist to know when such was needed, and to generate new gates and signales to handle what's missing.	steve	More...				over 25 years ago
Add the nobufz function to eliminate bufz objects, Object links are marked with direction, constant propagation is more careful will wide links, Signal folding is aware of attributes, and the XNF target can dump UDP objects based on LCA attributes.	steve	More...				over 25 years ago
Elaborate UDP devices, Support UDP type attributes, and pass those attributes to nodes that are instantiated by elaboration, Put modules into a map instead of a simple list.	steve	More...				over 25 years ago
Parse UDP primitives all the way to pform.	steve	More...				over 25 years ago
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.	steve	More...				over 25 years ago
Give anonymous modules a name when elaborated.	steve	More...				over 25 years ago
Add -f flags for generic flag key/values.	steve	More...				over 25 years ago
Add the sigfold function that unlinks excess signal nodes, and add the XNF target.	steve	More...				over 25 years ago
Introduce netlist optimizations with the cprop function to do constant propogation.	steve	More...				over 25 years ago
Handle while loops.	steve	More...				over 25 years ago
Check net ranges in declarations.	steve	More...				over 25 years ago
Add support it vvm target for level-sensitive triggers (i.e. the Verilog wait). Fix display of $time is format strings.	steve	More...				over 25 years ago
Add vvm library.	steve	More...				over 25 years ago
Oops, forgot return from operator<<	steve	More...				over 25 years ago
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.	steve	More...				over 25 years ago
Ignore generated dep directory.	steve	More...				over 25 years ago
Calculate expression widths at elaboration time.	steve	More...				over 25 years ago
Handle procedural conditional, and some of the conditional expressions.	steve	More...				over 25 years ago
Properly dump 0 length numbers.	steve	More...				over 25 years ago
Make sure dep is a directory.	steve	More...				over 25 years ago

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