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Analyzed about 8 hours ago. based on code collected about 8 hours ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Sep 05, 2024 — Sep 05, 2025 Showing page 12 of 303 Search / Filter on:
Merge pull request #3532 from cyyself/remove_b_zk	Jiuyang Liu	More...				almost 2 years ago
Remove Scalar Crypto and BitManip	Yangyu Chen	More...				almost 2 years ago
Remove Scalar Crypto and BitManip	Yangyu Chen	More...				almost 2 years ago
Merge pull request #3530 from chipsalliance/chisel5p1	Jiuyang Liu	More...				almost 2 years ago
Bump to Chisel 5.1	Jiuyang Liu	More...				almost 2 years ago
Merge pull request #3507 from chipsalliance/chisel_source	Jiuyang Liu	More...				almost 2 years ago
add sonatype snapshots repo for test chisel releases (#3527)	Jiuyang Liu	More...				almost 2 years ago
Fix r_pte update condition when S2 PTE cache hit (#3525) (#3526)	Jiuyang Liu	More...				almost 2 years ago
Fix r_pte update condition when S2 PTE cache hit (#3525)	Sihao Liu	More...				almost 2 years ago
Merge pull request #3523 from chipsalliance/mergify/bp/master/pr-3520	Jerry Zhao	More...				almost 2 years ago
Merge pull request #3520 from abejgonzalez/delay-queue	Jerry Zhao	More...				almost 2 years ago
Add docstrings	abejgonzalez	More...				almost 2 years ago
Add docstrings	abejgonzalez	More...				almost 2 years ago
Add DelayQueue variations	abejgonzalez	More...				almost 2 years ago
Add DelayQueue variations	abejgonzalez	More...				almost 2 years ago
Remove Chisel 3.6 support (#3515)	Jiuyang Liu	More...				almost 2 years ago
Fix RoCCCSRIO bidir (#3518)	mergify[bot]	More...				almost 2 years ago
Merge pull request #3516 from chipsalliance/jerryz123-patch-2	Jerry Zhao	More...				almost 2 years ago
Fix RoCCCSRIO bidir	Jerry Zhao	More...				almost 2 years ago
Synchronize ext-ints within the ibus domain	Jerry Zhao	More...				almost 2 years ago
Add SimpleLazyRawModule	Jerry Zhao	More...				almost 2 years ago
Fix intsynccrossings not receiving a clock	Jerry Zhao	More...				almost 2 years ago
Fix any unassigned clocks due to removal of implicit clock from BaseSubsystem	Jerry Zhao	More...				almost 2 years ago
Fix int clock crossings to use CLINT/PLIC domains	Jerry Zhao	More...				almost 2 years ago
Rename trace crossing nodes to crossing nodes	Jerry Zhao	More...				almost 2 years ago
Generalize WithNBigCores to support clustered cores	Jerry Zhao	More...				almost 2 years ago
Add documentation to DCache about datapath of meta/data arbiter (#3510)	Jiuyang Liu	More...				almost 2 years ago
Switch to separate cluster-local bus locations	Jerry Zhao	More...				almost 2 years ago
Add tile_reset_domain alias to element_reset_domain in TilePRCIDomain	Jerry Zhao	More...				almost 2 years ago
Switch to SortedMap for tile node maps	Jerry Zhao	More...				almost 2 years ago

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