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Analyzed about 11 hours ago. based on code collected about 11 hours ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Sep 05, 2024 — Sep 05, 2025 Showing page 302 of 303 Search / Filter on:
fixing output enable signals for data/tag SRAMs	Rimas Avizienis	More...				almost 14 years ago
more itlb/dtlb/ptw fixes	Rimas Avizienis	More...				almost 14 years ago
more tlb/ptw debugging	Rimas Avizienis	More...				almost 14 years ago
updated itlb	Rimas Avizienis	More...				almost 14 years ago
dcache/dtlb overhaul	Rimas Avizienis	More...				almost 14 years ago
checkpoint	Rimas Avizienis	More...				almost 14 years ago
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB	Rimas Avizienis	More...				almost 14 years ago
added misaligned instruction check, cleaned up badvaddr handling	Rimas Avizienis	More...				almost 14 years ago
access faults now write badvaddr PCR register with faulting address	Rimas Avizienis	More...				almost 14 years ago
moved exception handling from ex stage in dpath to mem stage in ctrl	Rimas Avizienis	More...				almost 14 years ago
fixed eret instruction	Rimas Avizienis	More...				almost 14 years ago
more tlb/ptw fixes	Rimas Avizienis	More...				almost 14 years ago
cleanup before adding dtlb	Rimas Avizienis	More...				almost 14 years ago
more itlb integration & cleanup	Rimas Avizienis	More...				almost 14 years ago
cleanup, fixes, initial commit for dtlb.scala	Rimas Avizienis	More...				almost 14 years ago
integrating ITLB & PTW	Rimas Avizienis	More...				almost 14 years ago
fix for flushed div/mul instructions	Rimas Avizienis	More...				almost 14 years ago
changed caches to use separate sram modules for tag and data arrays	Rimas Avizienis	More...				almost 14 years ago
cleanup	Rimas Avizienis	More...				almost 14 years ago
fixed eret instruction, hello world runs	Rimas Avizienis	More...				almost 14 years ago
dcache fixes - all tests and ubmarks pass, hello world still broken	Rimas Avizienis	More...				almost 14 years ago
fixes to exception and dcache miss/blocked handling	Rimas Avizienis	More...				almost 14 years ago
fixes for div/mul hazard checking + cleanup	Rimas Avizienis	More...				almost 14 years ago
dcache fix	Rimas Avizienis	More...				almost 14 years ago
dcache loads working - 1/2 cycle load/use delay depending on load type	Rimas Avizienis	More...				almost 14 years ago
dcache loads working - 1/2 cycle load/use delay depending on load type	Rimas Avizienis	More...				almost 14 years ago
pipeline changes for replay on dcache miss	Rimas Avizienis	More...				almost 14 years ago
interface cleanup, major pipeline changes	Rimas Avizienis	More...				almost 14 years ago
dcache fixes	Rimas Avizienis	More...				almost 14 years ago
dcache tweaks	Rimas Avizienis	More...				almost 14 years ago

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