Analyzed
about 6 hours
ago.
based on code collected
about 6 hours
ago.
Project Summary
A FPGA friendly 32 bit RISC-V CPU implementation
In a Nutshell, VexRiscv...
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has a well established, mature codebase
maintained by a large development team
with decreasing Y-O-Y commits -
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took an estimated 22 years of effort (COCOMO model)
starting with its first commit in March, 2017
ending with its most recent commit 2 months ago
Quick Reference
https://github.com/SpinalHDL/Vex...
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Poor security track-record
Favorable security track-record
Vulnerability Exposure Index
Many reported vulnerabilities
Few reported vulnerabilities
Did You Know...
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30 Day SummaryAug 5 2025 — Sep 4 2025
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12 Month SummarySep 4 2024 — Sep 4 2025
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