Analyzed
over 2 years
ago.
based on code collected
almost 3 years
ago.
Project Summary
A FPGA friendly 32 bit RISC-V CPU implementation
In a Nutshell, VexRiscv...
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has a young, but established codebase
maintained by a large development team
with stable Y-O-Y commits -
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took an estimated 15 years of effort (COCOMO model)
starting with its first commit in March, 2017
ending with its most recent commit almost 3 years ago
Quick Reference
https://github.com/SpinalHDL/Vex...
Project Security
Vulnerabilities per Version ( last 10 releases )
There are no reported vulnerabilities
Project Vulnerability Report
Security Confidence Index
Poor security track-record
Favorable security track-record
Vulnerability Exposure Index
Many reported vulnerabilities
Few reported vulnerabilities
Did You Know...
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30 Day SummarySep 10 2019 — Oct 10 2019
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12 Month SummaryOct 10 2018 — Oct 10 2019
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