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Tiny C Compiler

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  No analysis available

TinyCC (aka TCC) is a small but hyper fast C compiler. Unlike other C compilers, it is meant to be self-sufficient: you do not need an external assembler or linker because TCC does that for you. TCC compiles so fast that even for big projects Makefiles may not be necessary. TCC not only supports ... [More] ANSI C, but also most of the ISO C99 and ISO C11 standard and also many GNUC extensions. TCC can also be used to make C scripts, i.e. pieces of C source that you run as a script. Compilation is so fast that your script will be as fast as if it was an executable. TCC can also automatically generate memory and bound checks while allowing all C pointers operations. With libtcc, you can use TCC as a backend for dynamic code generation. [Less]

0 lines of code

28 current contributors

0 since last commit

7 users on Open Hub

Activity Not Available
4.0
   
I Use This
Mostly written in language not available
Licenses: gpl

NEORV32

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  Analyzed about 6 hours ago

A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

41.8K lines of code

0 current contributors

2 days since last commit

1 users on Open Hub

Very High Activity
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

meta-riscv

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  Analyzed about 21 hours ago

OpenEmbedded/Yocto layer for RISC-V Architecture

146 lines of code

0 current contributors

18 days since last commit

1 users on Open Hub

Low Activity
0.0
 
I Use This

serv

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  Analyzed about 15 hours ago

SERV - The SErial RISC-V CPU

5.72K lines of code

6 current contributors

14 days since last commit

1 users on Open Hub

Low Activity
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

PULP Platform

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  Analyzed about 1 hour ago

An open-source microcontroller system based on RISC-V

2.65M lines of code

64 current contributors

about 14 hours since last commit

0 users on Open Hub

High Activity
0.0
 
I Use This
Licenses: No declared licenses
Tags risc_v

RISC-V BOOM

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  Analyzed about 22 hours ago

Berkeley Out-of-Order Machine, a out of order CPU based on the risc-v instruction set architecture.

30.4K lines of code

14 current contributors

about 1 month since last commit

0 users on Open Hub

Moderate Activity
0.0
 
I Use This
Licenses: No declared licenses

Rocket-Chip

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  Analyzed about 22 hours ago

Rocket Chip is Berkeley's RISC-V based SOC generator. The open-source release is capable of generating a multi-core system with Rocket scalar cores, Z-Scale control processors, and a coherent memory system.

44.5K lines of code

41 current contributors

30 days since last commit

0 users on Open Hub

Moderate Activity
0.0
 
I Use This
Licenses: No declared licenses

SHAKTI

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  Analyzed 1 day ago

IIT Madras Shakti Open Source Processor family - based on the RISCV ISA

401K lines of code

8 current contributors

over 4 years since last commit

0 users on Open Hub

Inactive
0.0
 
I Use This
Licenses: No declared licenses
Tags cpu risc_v

ReonV

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  Analyzed about 7 hours ago

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

473K lines of code

0 current contributors

over 1 year since last commit

0 users on Open Hub

Very Low Activity
0.0
 
I Use This
Licenses: No declared licenses

VexRiscv

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  Analyzed 1 day ago

A FPGA friendly 32 bit RISC-V CPU implementation

87.6K lines of code

8 current contributors

21 days since last commit

0 users on Open Hub

Moderate Activity
0.0
 
I Use This
Licenses: No declared licenses
Tags cpu risc_v