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Analyzed 8 days ago. based on code collected 8 days ago.

Project Summary

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations.

DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and simulations are supported thanks to integration with FreeHDL and Icarus Verilog.
Output is may be presented with wide variety of graph and tabular charts.

The package consists of two utilities:
Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®.
Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than

Tags

analog circuit digital electronics hardware logic modeling qt simulation simulator verilog vhdl

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In a Nutshell, Qucs...

GNU General Public License v2.0 or later
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These details are provided for information only. No information here is legal advice and should not be used as such.

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This Project has No vulnerabilities Reported Against it

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Languages

Languages?height=75&width=75
XML
53%
C++
31%
TeX/LaTeX
9%
12 Other
7%

30 Day Summary

Jan 14 2018 — Feb 13 2018

12 Month Summary

Feb 13 2017 — Feb 13 2018
  • 0 Commits
    Down -294 (100%) from previous 12 months
  • 0 Contributors
    Down -10 (100%) from previous 12 months

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3 users rate this project:
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