Tags : Browse Projects

Select a tag to browse associated projects and drill deeper into the tag cloud.

Qucs

Compare

  Analyzed 11 months ago

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations. DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and ... [More] simulations are supported thanks to integration with FreeHDL and Icarus Verilog. Output is may be presented with wide variety of graph and tabular charts. The package consists of two utilities: Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®. Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than [Less]

504K lines of code

10 current contributors

over 1 year since last commit

10 users on Open Hub

Activity Not Available
4.66667
   
I Use This

GHDL

Compare

  Analyzed 11 months ago

GHDL is a complete VHDL simulator, using the GCC technology. GHDL implements the VHDL language according to the IEEE 1076-1987 or the IEEE 1076-1993 standard. GHDL compiles VHDL files and creates a binary which simulates (or executes) your design. New GHDL development is at ... [More] http://sourceforge.net/projects/ghdl-updates/ and includes significant VHDL-2008 support (in ghdl-0.33, released Oct 2015). The original ghdl page was : http://ghdl.free.fr/ The original download page was : http://ghdl.free.fr/download.html [Less]

677K lines of code

11 current contributors

12 months since last commit

7 users on Open Hub

Activity Not Available
4.0
   
I Use This

atom

Compare

  Analyzed almost 6 years ago

Atom is a DSL embedded in Haskell used to describe synchronous reactive software systems, primarily intended for realtime control applications. Based on conditional term rewriting, an atom description is composed of a set of rules that defines the state transition behavior of the system at periodic intervals.

3.42K lines of code

0 current contributors

over 9 years since last commit

5 users on Open Hub

Activity Not Available
0.0
 
I Use This

HDMI2USB

Compare

Claimed by TimVideos.us - Live Event S... Analyzed about 1 month ago

Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.

1.05M lines of code

4 current contributors

11 months since last commit

2 users on Open Hub

Activity Not Available
0.0
 
I Use This

vunit-hdl

Compare

  Analyzed about 1 month ago

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing ... [More] methodologies by supporting a "test early and often" approach through automation. [Less]

39.3K lines of code

9 current contributors

4 months since last commit

2 users on Open Hub

Activity Not Available
5.0
 
I Use This

OSVVM

Compare

  Analyzed 3 months ago

Open Source VHDL Verification Methodology (OSVVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as ... [More] needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. [Less]

9.62K lines of code

1 current contributors

7 months since last commit

2 users on Open Hub

Activity Not Available
5.0
 
I Use This

FPGALink

  Analyzed about 1 month ago

The aim of the FPGALink project is to provide a hardware abstraction layer for hardware involving an FPGA connected to a computer over USB, to abstract core functionality like FPGA-programming and subsequent host-FPGA communication. It doesn't matter whether the hardware uses an AVR, an FX2LP or an ... [More] ARM-based micro for its USB interface. It doesn't matter whether the FPGA is from Xilinx or Altera or Lattice or whomever. It doesn't matter whether the interface between them is a fast 43MiB/s parallel synchronous interface, a much slower EPP interface or some sort of USART connection. The cross-platform, cross-language host-side API is the same, and the FPGA-side (VHDL or Verilog) FIFO interface is the same, so you can easily port your design to a new FPGA devkit or to your own custom PCB. [Less]

32.8K lines of code

0 current contributors

over 1 year since last commit

1 users on Open Hub

Activity Not Available
0.0
 
I Use This
Licenses: GPL-2.0, GPL-3.0+, LGPL-3.0+

Kactus2

Compare

  Analyzed 3 months ago

Kactus2 is the first graphical open source IP-XACT toolset to design embedded products, especially FPGA-based MP-SoCs. It provides easier IP reusabilility and practical HW/SW abstraction for easier application SW development.

283K lines of code

9 current contributors

3 months since last commit

1 users on Open Hub

Activity Not Available
0.0
 
I Use This

schifra

Compare

  Analyzed 5 months ago

Schifra is a very robust, highly optimized and extremely configurable Reed-Solomon error correcting code library for both software and IP core based applications with implementations in C++ and VHDL. Schifra supports standard, shortened and punctured Reed-Solomon codes. It also has support for ... [More] stacked product codes and interleaving. General Features * Errors and Erasures * Supported Symbol Sizes - 2 to 32 bits * Variable Code Block Length * User defined primitive polynomial and finite field * Accurate and Validated Reed-Solomon Codecs - Complete combinatorial errors and erasures unit testing [Less]

7.17K lines of code

1 current contributors

5 months since last commit

1 users on Open Hub

Activity Not Available
5.0
 
I Use This

cocotb

Compare

  Analyzed 3 months ago

Coroutine Co-simulation Test Bench

21.4K lines of code

13 current contributors

5 months since last commit

1 users on Open Hub

Activity Not Available
3.0
   
I Use This