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GHDL

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  Analyzed 1 day ago

GHDL is an open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL provides full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 revision. GHDL allows you to analyse and ... [More] elaborate sources for generating machine code from your design. [Less]

928K lines of code

18 current contributors

5 days since last commit

10 users on Open Hub

Moderate Activity
4.66667
   
0 Reviews
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Mostly written in VHDL
Licenses: gpl
Tags ada compiler hardware-description simulator vhdl

Qucs

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  Analyzed 1 day ago

Qucs is a integrated circuit simulator for rapid development of analog and digital circuits and wide range of simulations. DC, AC, S-parameter, noise and transient analysis are supported, mathematical equations and use of a subcircuit hierarchy are available. Digital circuit models and ... [More] simulations are supported thanks to integration with FreeHDL and Icarus Verilog. Output is may be presented with wide variety of graph and tabular charts. The package consists of two utilities: Qucs, elegant and powerfull GUI for designing and simulating circuits, with point-and-click interface, based on Qt® by Digia®. Qucsator, a command line circuit simulator. It takes a network list in a certain format as input and outputs a Qucs dataset. May also be used by applications other than [Less]

879K lines of code

8 current contributors

3 months since last commit

10 users on Open Hub

Moderate Activity
4.66667
   
0 Reviews
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Mostly written in TypeScript
Licenses: gpl
Tags analog circuit digital electronics hardware logic modeling qt simulation simulator verilog vhdl

VUnit HDL

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  Analyzed about 5 hours ago

VUnit is an open source unit testing framework for VHDL/SystemVerilog released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn't replace but rather complements traditional testing ... [More] methodologies by supporting a "test early and often" approach through automation. [Less]

82.9K lines of code

25 current contributors

4 months since last commit

3 users on Open Hub

Very Low Activity
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: mozilla_p...
Tags library logging open-source python reporting simulation systemverilog test-driven-design test-driven-development testing verification verilog 1 more...

OSVVM

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  Analyzed about 4 hours ago

Open Source VHDL Verification Methodology (OSVVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as ... [More] needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models. [Less]

140K lines of code

1 current contributors

about 1 month since last commit

3 users on Open Hub

High Activity
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: apache_2
Tags asic fpga library logging open-source randomization reporting simulation testing verification vhdl

HDMI2USB

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Claimed by TimVideos.us - Live Event S... Analyzed about 1 year ago

Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data.

121M lines of code

13 current contributors

over 1 year since last commit

2 users on Open Hub

Activity Not Available
0.0
 
0 Reviews
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Mostly written in coq
Licenses: apache_2
Tags camera capturecard conference digital dvi electronics firmware fpga hardware hdmi mjpeg pcb 8 more...

nvc

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  Analyzed about 10 hours ago

VHDL compiler and simulator

320K lines of code

0 current contributors

about 23 hours since last commit

2 users on Open Hub

High Activity
0.0
 
0 Reviews
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Mostly written in C
Licenses: No declared licenses
Tags compiler fpga simulator verification vhdl

pyVHDLModel

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  Analyzed 1 day ago

An abstract language model of VHDL written in Python.

7.44K lines of code

0 current contributors

4 months since last commit

2 users on Open Hub

Low Activity
5.0
 
0 Reviews
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Mostly written in Python
Licenses: apache_2
Tags documentobjectmodel dom model python vhdl

Electronic Design Automation Abstraction (EDA²)

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  Analyzed about 1 hour ago

39.7K lines of code

0 current contributors

about 2 months since last commit

2 users on Open Hub

Moderate Activity
0.0
 
0 Reviews
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Mostly written in Python
Licenses: No declared licenses
Tags eda implementation layers simulation stack synthesis verilog vhdl

PicoBlaze-Library

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  Analyzed about 22 hours ago

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

15.6K lines of code

0 current contributors

almost 10 years since last commit

1 users on Open Hub

Inactive
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: apache_2
Tags 8-bit altera kcpsm library opbasm picoblaze synthesis system-on-chip vhdl xilinx

PoC-Library

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  Analyzed about 19 hours ago

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

60.2K lines of code

2 current contributors

3 months since last commit

1 users on Open Hub

Moderate Activity
5.0
 
0 Reviews
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Mostly written in VHDL
Licenses: apache_2
Tags aldec altera arithmetic cross-platform fifo fpga i2c ipcore lattice library mentorgraphics open-source 8 more...