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Analyzed 1 day ago. based on code collected 1 day ago.

Commit Message	Contributor	Files Modified	Lines Added	Lines Removed	Code Location	Date
Sep 02, 2024 — Sep 02, 2025 Showing page 300 of 302 Search / Filter on:
require writes to memory to be uninterrupted	Andrew Waterman	More...				over 13 years ago
made tohost/fromhost 64 bits wide	Andrew Waterman	More...				over 13 years ago
move PCR writes to WB stage	Andrew Waterman	More...				over 13 years ago
remove second RF write port	Andrew Waterman	More...				over 13 years ago
fix WAW hazard handling	Andrew Waterman	More...				over 13 years ago
reduce superfluous replays	Andrew Waterman	More...				over 13 years ago
validate BTB address and use BTB for J/JAL/JR/JALR	Andrew Waterman	More...				over 13 years ago
remove datapath register resets resets	Andrew Waterman	More...				over 13 years ago
fixes for correct verilog generation	Andrew Waterman	More...				over 13 years ago
fix multiplier bug	Andrew Waterman	More...				over 13 years ago
vlsi verilog compiles now but doesn't simulate	Andrew Waterman	More...				over 13 years ago
parameterized multiplier unrolling	Andrew Waterman	More...				over 13 years ago
booth multiplier	Andrew Waterman	More...				over 13 years ago
fix divider for RV32	Andrew Waterman	More...				over 13 years ago
add dummy mul_rdy signal	Andrew Waterman	More...				over 13 years ago
improve ALU and fix revealed emulator bug	Andrew Waterman	More...				over 13 years ago
fix multiplier for rv32	Andrew Waterman	More...				over 13 years ago
hellacache now works	Andrew Waterman	More...				over 13 years ago
hellacache returns!	Andrew Waterman	More...				over 13 years ago
new mftx instruction format	Yunsup Lee	More...				over 13 years ago
work in progress on hellacache	Andrew Waterman	More...				over 13 years ago
Support cache->cpu nacks one cycle after request	Andrew Waterman	More...				over 13 years ago
Don't replay from EX stage.	Andrew Waterman	More...				over 13 years ago
code cleanup/parameterization	Andrew Waterman	More...				over 13 years ago
Automatically infer rocketCAM address width	Andrew Waterman	More...				over 13 years ago
made setReadLatency argument a parameter defined in consts.scala	Rimas Avizienis	More...				over 13 years ago
icache/dcache tag+data arrays now implemented using Mem4() however there seems to be a bug - readLatency needs to be set to 0 for C model to work, and 1 for Verilog model.	Rimas Avizienis	More...				over 13 years ago
caches now use Mem4() memories for tag+data arrays	Rimas Avizienis	More...				over 13 years ago
tweaks to cache/SRAM interface for TSMC65 SRAMs	Rimas Avizienis	More...				almost 14 years ago
changed branch addr generation to get it off critical path	Rimas Avizienis	More...				almost 14 years ago

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