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Commits : Listings

Analyzed 1 day ago. based on code collected 1 day ago.
Sep 02, 2024 — Sep 02, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
renamed SRAM modules to match TSMC65 MC generated SRAMs More... almost 14 years ago
fixed console i/o More... almost 14 years ago
Merge branch 'master' of github.com:ucb-bar/riscv-rocket More... almost 14 years ago
bugfixes due to new hcl jar file More... almost 14 years ago
queue data type is now templated More... almost 14 years ago
more cleanup More... almost 14 years ago
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl More... almost 14 years ago
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions More... almost 14 years ago
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction More... almost 14 years ago
writes of PC weren't being sign extended More... almost 14 years ago
cleanup More... almost 14 years ago
more amo fixes, added more options to testharness to control debug messages More... almost 14 years ago
AMOADD, AMOAND, AMOOR, AMOSWAP working More... almost 14 years ago
updated riscv-bmarks and riscv-tests to build with new toolchain More... almost 14 years ago
made eret instruction take an illegal inst exception when ET is set More... almost 14 years ago
added ei and di instructions More... almost 14 years ago
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs More... almost 14 years ago
added IPIs and timer interrupts More... almost 14 years ago
synced up with supervisor mode state in latest ISA simulator More... almost 14 years ago
more cache fixes, more test harness debug output More... almost 14 years ago
cache/tlb bugfixes, increased memory size to 256meg More... almost 14 years ago
fixed typo that broke illegal instruction exception More... almost 14 years ago
regenerated instruction encodings using parse-opcodes More... almost 14 years ago
timer interrupt fixes More... almost 14 years ago
added timer interrupt support More... almost 14 years ago
added ld/st misaligned exceptions More... almost 14 years ago
added checks for addresses > physical memory size, increased memsize to 64M More... almost 14 years ago
cache optimizations, cleanup, and testharness improvement More... almost 14 years ago
fixing output enable signals for data/tag SRAMs More... almost 14 years ago
more itlb/dtlb/ptw fixes More... almost 14 years ago