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SSRV (Super-Scalar RISC-V)
S
Analyzed 2 days ago
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Licenses:
No declared licenses
RSD
R
Analyzed 2 days ago
RSD: RISC-V Out-of-Order Superscalar Processor
Licenses:
No declared licenses
Toooba
T
Analyzed 2 days ago
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Licenses:
No declared licenses
openc910
O
Analyzed 7 days ago
Alibaba c910 high performance RISC-V core.
Licenses:
No declared licenses
cgen
C
No analysis available
CGEN, the Cpu tools GENerator
CGEN (pronounced seejen) is a framework for developing generators of CPU-related tools such as assemblers, disassemblers and simulators. It specifies a description language for describing the architecture and organization of a CPU without reference to any particular
Mostly written in language not available
Licenses:
gpl
vroom
V
Analyzed 2 days ago
a very high end RISC-V implementation , its goal is to be a cloud server class implementation.
Licensed under the GPL, with a commercial license also available.
Licenses:
No declared licenses
pyperfcounter
P
No analysis available
pyperfcounter is a ctypes-based Python wrapper of Linux's new performance counter subsystem. Currently you have to patch your kernel to get perfcounter support: http://people.redhat.com/mingo/perfcounters/
Mostly written in language not available
Licenses:
No declared licenses
XiangShan
X
Analyzed about 3 hours ago
XiangShan (香山) is an open-source high-performance RISC-V processor project.
Licenses:
apache_2
CPUID CLI
Analyzed 1 day ago
A simple command-line utility to dump and/or decode CPUID information on x86/x86_64 processors.
This tool strictly follows the specifications provided by Intel and AMD. Some support has been added for other vendors, but results from non-Intel/non-AMD chips should not be relied upon.