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XiangShan
X
Analyzed about 1 hour ago
XiangShan (香山) is an open-source high-performance RISC-V processor project.
Licenses:
apache_2
RISC-V BOOM
R
Analyzed about 5 hours ago
Berkeley Out-of-Order Machine, a out of order CPU based on the risc-v instruction set architecture.
Licenses:
No declared licenses
riscy-OOO
R
Analyzed about 17 hours ago
RiscyOO: RISC-V Out-of-Order Processor
Licenses:
No declared licenses
SSRV (Super-Scalar RISC-V)
S
Analyzed about 12 hours ago
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Licenses:
No declared licenses
RSD
R
Analyzed about 20 hours ago
RSD: RISC-V Out-of-Order Superscalar Processor
Licenses:
No declared licenses
Toooba
T
Analyzed about 21 hours ago
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Licenses:
No declared licenses
openc910
O
Analyzed over 1 year ago
Alibaba c910 high performance RISC-V core.
Licenses:
No declared licenses
vroom
V
Analyzed 1 day ago
a very high end RISC-V implementation , its goal is to be a cloud server class implementation.
Licensed under the GPL, with a commercial license also available.
Licenses:
No declared licenses