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Commits : Listings

Analyzed 1 day ago. based on code collected 1 day ago.
Sep 02, 2024 — Sep 02, 2025
Commit Message Contributor Files Modified Lines Added Lines Removed Code Location Date
Split RocketConfigs into separate file
Jerry Zhao
More... about 1 year ago
Merge pull request #3652 from chipsalliance/rvv_isastrs
Jerry Zhao
More... about 1 year ago
Add new config-fragements
Kevin99214
More... about 1 year ago
Allow non-V implementations of vector units, with Zve/Zvl extensions
Jerry Zhao
More... about 1 year ago
Merge commit 'ea9979b1'
Hansung Kim
More... about 1 year ago
Merge pull request #3651 from chipsalliance/ptw_leaf
Jerry Zhao
More... about 1 year ago
PTW: traverse check GPA bits higher than HGATP mode only if leaf
John Ingalls
More... about 1 year ago
Merge pull request #3641 from chipsalliance/naming
Jerry Zhao
More... about 1 year ago
Merge pull request #3648 from chipsalliance/tile_int_domain
Jerry Zhao
More... about 1 year ago
Interrupts coming outwards from the Tile should cross into a toPlicDomain
Jerry Zhao
More... about 1 year ago
Merge pull request #3642 from chipsalliance/empty_diplomacy
Jerry Zhao
More... about 1 year ago
[cluster] Add missing clock group connection for clbus
Hansung Kim
More... about 1 year ago
Add deprecated accessors to diplomacy package components
Jerry Zhao
More... about 1 year ago
Move dts/resources to new resources subpackage
Jerry Zhao
More... about 1 year ago
Move clockCrossing types into prci
Jerry Zhao
More... about 1 year ago
Merge pull request #3639 from chipsalliance/named_domains
Jerry Zhao
More... over 1 year ago
Set desiredName for ClockDomains of rom/plic/clint
Jerry Zhao
More... over 1 year ago
Set desiredName for many system components
Jerry Zhao
More... over 1 year ago
Add generateSynchronousDomain API to set domain desiredName
Jerry Zhao
More... over 1 year ago
Set ClockDomain desiredName by ClockParameters name
Jerry Zhao
More... over 1 year ago
Merge pull request #3634 from Kevin99214/APBToTLfix
Jerry Zhao
More... over 1 year ago
Add IO Connections for Custom User Field in TL Channels within Xbar module Please refer to the issue page below. https://github.com/ucb-bar/chipyard/issues/1888
Sungkeun Kim
More... over 1 year ago
Update APBtoTL scala to not flip apb address when doing conversion
Kevin Qin
More... over 1 year ago
Merge pull request #3631 from chipsalliance/cp_fpu
Jerry Zhao
More... over 1 year ago
Allow pipeline coprocessor accesses into FPU
Jerry Zhao
More... over 1 year ago
Support configurable ifpu and fpmu latency in FPU
Jerry Zhao
More... over 1 year ago
Merge pull request #3599 from chipsalliance/ifv
Jerry Zhao
More... over 1 year ago
Fix vector debug trace
Jerry Zhao
More... over 1 year ago
Merge branch 'dev' of https://github.com/chipsalliance/rocket-chip into upstream
Richard Yan
More... over 1 year ago
Don't gate of ctrl.vec with vill
Jerry Zhao
More... over 1 year ago